Buffer memory systems are commonly used as an interface to couple a host computer and a mass storage device such as a disc drive. One difficulty with such an interface is that data passed to or from the mass storage device is in a serial format, for example data passed to or from a read/write head of a disc drive, while within the computer it is passed along a parallel data bus. Another difficulty is that the computer processes data much more rapidly than the mass storage device is able to store or retrieve it. Thus, the buffer memory system must convert data from a parallel to a serial format and must match the rate with which the data is written to or read from the mass storage device to the much greater rate of the computer by temporarily storing data being transferred between the computer and the mass storage device. A typical buffer memory system includes a buffer memory for temporarily storing data, and a controller for translating or mapping blocks of data from logical block addresses used by a central processing unit (CPU) in the computer to corresponding physical addresses in the buffer memory. The buffer memory generally includes one or more data storage devices, such as random access memories or memory chips (RAM chips). RAM chips are integrated circuit memory chips that have an array of memory cells arranged in rows and columns. FIG. 1 diagrammatically illustrates a conventional buffer memory having a pair of arrays 100, 105 each having 256 column addresses by 4096 row addresses. The column addresses are further divided into 16 groups of 16 columns each to enable data to be stored in blocks of data known as paragraphs consisting of 16 words of 16 bits each. For example, a first paragraph (PARA 0) 106 having a logical address of 0, is mapped to a first row (row 0), in a first group of columns (columns 0 through 15), a second paragraph (PARA 1) 107 is mapped to row 1 of columns 0 through 15, and so on. After the last row in the first group of columns has been reached, for example, after the 4096.sup.th paragraph (PARA 4095) 108 has been mapped to row 4095, the row address loops back to row 0 and the column address is incremented to the second group of columns, that is to columns 16 through 31.
Generally, the controller also includes a scheme for checking the integrity of data stored and recovered from the disc drive. In one such scheme, a bit-wise EXCLUSIVE-OR (XOR) operation is performed on each word in a paragraph of data received from the computer. The result of this XOR operation, known as a parity word, is appended to the paragraph stored in the buffer memory and is then transferred to the mass storage device. When a previously stored paragraph of data is recovered from the mass storage device the XOR operation is repeated and the result compared with the stored parity word. If the result is the same, then the recovered data is presumed to be valid, if not an error correcting routine can be invoked to identify and correct the erroneous bit or bits. One problem with this data integrity scheme is that because the parity word occupies a physical address in the RAM chip it renders the corresponding logical address unavailable for addressing data, thus resulting in noncontiguous logical addresses for sequential blocks of data. This is undesirable, since non-contiguous logical addresses increase the time, measured by the number of cycles of a computer's clock, necessary for the computer's CPU to advance from one logical address to the next noncontiguous logical address, thereby impeding operation of the CPU. Also, noncontiguous logical addresses complicate the mapping process, reducing the bandwidth of the buffer memory system. The term bandwidth is commonly used in the field of computer memory to denominate how much information can be transferred to or from the buffer memory in given period.
One partial solution, shown in FIG. 1 uses a scheme known as longitudinal redundancy code (LRC). As with the data integrity scheme described earlier a bit-wise XOR operation is performed on each word in a paragraph to generate a parity word for the paragraph, known here as a LRC-word. However, unlike in the earlier data integrity scheme, the LRC-word is not appended to the paragraph, but is stored separately in the last group of columns, i.e., columns 241 to 256, which are reserved exclusively for parity information. Preferably, the LRC-word for a paragraph is stored in the same row to reduce command overhead, which is the processing time needed by the controller to execute an instruction. Reducing command overhead increases the available bandwidth of the system for useful tasks. Storing the LRC-word in the same row saves the time needed to move from one row address to another, typically about seven clock cycles. An exemplary process for carrying out this scheme will be described with reference to FIG. 1. Beginning with column 241, the column address for a LRC-word is incremented for each paragraph in the same row. For example, the LRC-word for the first paragraph 106 is stored at row 0, column 241, while the LRC-word for the second paragraph 107 is stored at row 1, column 241, and the LRC-word for a 4097.sup.th paragraph 109 is stored at row 0, column 242. Thus, the LRC-words are moved to the top end of the range of logical addresses, leaving a contiguous block of logical addresses available for addressing data.
The above approach works adequately for buffer memory systems having a single temporary storage device, such as a single RAM chip. However, a rapid increase in recent years in both the size of computer programs and in the data manipulated by them has led to the development of higher capacity mass storage devices. This in turn has created a demand for faster buffer memory systems having more buffer memory, to interface with them. Traditionally, increasing buffer memory has been accomplished by either increasing the capacity of the RAM chips or by adding more RAM chips to the buffer memory. Unfortunately, neither of these solutions is completely satisfactory. The first is unsatisfactory because the cost of RAM rises dramatically with increasing capacity, and in the highly competitive computer memory market it is undesirable to use more expensive, higher capacity RAM.
Similarly, a problem with the second solution i.e., adding more RAM chips, is that the relatively inexpensive, unsophisticated controllers used in conventional buffer memory systems generally limit the number of RAM chips that can be addressed by a single controller to one or two. Another problem with increasing the number of RAM chips is that for buffer memory systems using the data integrity scheme described above, in which all rows of the last group of columns are reserved for LRC-words, adding more RAM chips reintroduces noncontiguous logical addresses when crossing the chip boundary. By crossing the chip boundary it is meant the transition from the last physical address available for data on a first RAM chip to the first available physical address on a second RAM chip. Because all the rows in columns 241 to 256 of the first RAM 10 are reserved for LRC-words in moving to the second RAM 15, the controller must skip over the logical addresses corresponding to the physical addresses of these areas, resulting in noncontiguous logical addresses for sequential blocks of data.
Accordingly, there is a need for a faster buffer memory system with more buffer memory. There is also a need for a buffer memory system that provides contiguous logical addresses for sequential blocks of data mapped to different temporary storage devices, such as a number of RAM chips. There is a further need for a buffer memory system that includes a scheme for checking the integrity of data stored and recovered from a mass storage device. There is a still further need for a buffer memory system that includes an addressing and a data integrity scheme that increases the bandwidth of the buffer memory system. Finally, to be commercially feasible, it is desirable that the increase in buffer memory should be realizable with less expensive, smaller capacity RAM chips and with existing controllers.
The present invention provides a solution to these and other problems, and offers other advantages over the prior art.